Integrated circuits (ICs) can be implemented to perform a variety of functions. Some ICs can be programmed to perform specified functions. One example of an IC that can be programmed is a field programmable gate array (FPGA). An FPGA typically includes an array of programmable circuit blocks called “tiles.” These tiles may include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
In general, the elements within tiles are connected using wires of various lengths. Some wires connect a source located within a tile to a load located within the same tile. Other wires connect elements in different tiles. For example, the wire may connect a source located within a first tile with a load located within an adjacent or abutting tile. Still other wires connect a source located within a tile to a load located in a non-adjacent or non-abutting tile. For example, the wire may connect a source located in a first tile to a load located in a second tile, where the first and second tiles are separated by one or more intervening tiles.
Within the actual IC, wires exist in metal or conductive layers typically located above the layers of the IC used to form elements such as transistors, memory cells, and so forth. Wires that connect a source and a load in non-adjacent tiles travel over the intervening tile(s). These wires merely pass over the intervening tiles and have no interaction with the circuitry within these intervening tiles.
Electronic design automation (EDA) tools routinely render graphical representations of ICs. In many cases, the EDA tool generates a flat, e.g., 2-dimensional (2D), representation of the 3D IC structure. In general, elements of the physical IC are represented as objects within a data structure referred to as a device model of the IC. In the usual case, the EDA tool generates the 2D representation from the device model. For purposes of generating graphical representations of the IC, EDA tools have treated wires as belonging to the particular tile over which that wire is located or passes. This technique is sometimes used for programmable ICs such as FPGAs due to the tile array architecture of the programmable ICs.
As programmable ICs become larger and exhibit more diverse layouts, the ability to generate a device model from hardware description language and render a graphical representation of the device model become ever more useful. Unfortunately, generating a graphical representation of the device model of an IC becomes increasingly difficult as storage of the device model and the rendering operations require ever more resources of the EDA tool, thereby degrading performance.